The present invention relates to graphic display and more particularly to a graphic display method and apparatus for displaying graphics at high speed by parallel processing.
Graphic display processing generally includes display transversal which traces structured graphic data and which obtains a graphic command to designate a graphics, geometric processing including graphic coordinate transformation and clipping, and numerical processing such as intensity calculation using the equation of light reflection, and rendering for creating an image room geometrical information. In the present specification, geometrical processing such as graphic coordinate transformation and clipping, and numerical processing including intensity calculation using the equation of light reflection are referred to as graphic processing, which is one of the important factors to determine the graphic performance.
A first known conventional example is a graphic display device which performs graphic processing in a pipelined system to realize high speed display, as disclosed in Unexamined Japanese Patent Publication JP-A 64-992.
In this pipelined system, allocation of equal loads on the respective pipeline stages is difficult. If, especially, a heavy load is to be processed, graphic performance is limited by the stage concerned and other stages would be idle. Another problem is that transmission of information through the respective pipeline stages takes substantial time. Since the graphic display device usually processes various figures such as line segments and surfaces, it is required to determine the types of the figures at the respective pipeline stages and the time taken for this determination cannot be neglected.
Therefore, a system for processing a graphics using a plurality of processors in parallel is invented, as discussed in Computer Graphics, Vol. 24, No. 4 (Aug. 1990), pp. 299-307 as a second conventional example.
The system includes a plurality of processors (CPUs), a main memory, a rasterizing engine which produces an image from geometric information, a general I/O bus adapter, a main system bus connecting these elements, and an I/O unit. Graphic commands produced by some of the plurality of processors are sequentially allocated to other processors to perform the graphic processing operation. The result of this processing operation is delivered to the rasterizing engine where an image is produced and displayed.
In this case, since all the stages of the series of the graphic processing operations are performed by one processor, it does not occur that other processors become idle especially due to the processing of a heavy load as in the pipelined system. No transfer of data between the processors and no determination of the kind of a graphic are required at each processing operation to thereby realize high speed display.
For an attribute command designating the manner of display, a processor which has processed this command delivers the result to all other processors in order to reflect the result of the processing to other processors so as to prevent disorder in the attributes. To this end, the first-mentioned processor is required to be synchronized with other processors to thereby render the processing complicated and hence take substantial time for that processing.
Since the graphic commands are sequentially allocated to the processors, the loads on some processors increase to thereby reduce the overall performance if the times required for processing the graphic commands are greatly uneven.
A method of processing a graphics with a plurality of processors is known as a third conventional example, as discussed in Computer Graphics, Vol. 21, No. 4, (July 1897), pp. 197-204. The display list manager which delivers a graphic command to graphics arithmetic processors which process the graphics attaches a control bit indicative of the kind of a command and a method of control to the head of the graphic command and sends the result to the input bus. The graphics arithmetic processors take commands on the bus with priorities corresponding to the loads to be processed, refers to the control bit of the taken command, determines whether the command should be processed and processes a necessary command. When the graphics arithmetic processors output a signal, the processors determine an appropriate timing for the output. If the timing is too early, the processor delays sending the data to an image memory unit. According to this method, a display list manager produces the control bit, and adds it to the graphic command. The graphics arithmetic processor must refer to the control bit, determine the processing, and manage the output timing. As described above, the graphics arithmetic processors are dispersed and control the entire operation of the system, so that processing and hardware tend to be complicated.